The present invention relates to a semiconductor device, and in particular relates to a lateral-type high-voltage semiconductor device having an insulated gate structure.
In the explanation below and in the attached drawings, an “n” or “p” denoting a layer or region means that electrons or holes, respectively, are the majority carrier. Moreover, a “+” or “−” appended to an “n” or “p” means that the impurity concentration is higher or lower respectively than in a layer or region without such symbols appended.
FIG. 52 is a cross-sectional view showing the configuration of an IGBT (Insulated Gate Bipolar Transistor) of the prior art. As shown in FIG. 52, a SOI (Silicon On Insulator) substrate comprises a supporting substrate 1, buried oxide film 2, and semiconductor layer (n− drift region 3). The p base region 4, p+ contact region 5, and n+ emitter region 6 are provided in a surface region of the n− drift region 3. The n buffer region 11 and p+ collector region 12 are provided in a surface region of the n− drift region 3, at a distance from the p base region 4.
The emitter electrode 7 is in contact with the p+ contact region 5 and n+ emitter region 6. The gate electrode 8 is provided, with the gate insulating film 9a intervening, on the surface of the p base region 4 between the n+ emitter region 6 and the n− drift region 3. The collector electrode 10 is in contact with the p+ collector region 12. The surface of the n− drift region 3 is covered by a LOCOS (Local Oxidation of Silicon) oxide film 9b. 
In the configuration shown in FIG. 52, when the p+ collector region 12 is replaced with an n-type low-resistivity region (n+ drain region), a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) configuration results. This unit cell structure is arranged in repetition according to the required current capacity (see for example Japanese Patent Publication No. 3473460 (paragraph [0011], FIG. 1), corresponding to U.S. Pat. No. 6,441,432 B1).
FIG. 53 is a cross-sectional view showing the configuration of a multicell-structure IGBT of the prior art. As shown in FIG. 53, a plurality of cells are arranged in repetition separated by a trench isolation portion. The trench isolation portion comprises an isolation trench 13, and a silicon region adjacent to the isolation trench 13 (and hereafter called an isolation silicon region) 14. The isolation trench 13 is formed by burying a trench reaching from the surface of the SOI substrate to the buried oxide film 2 with an oxide film or other insulating film. A structure in which the trench isolation portion is provided for each cell is also well known (see Japanese Patent Application Laid-open No. 2006-210865 (FIG. 1)).
FIG. 54 is a plane view showing the planar layout of an IGBT of the prior art. As shown in FIG. 54, the collector electrode 10 extends linearly. The gate electrode 8 comprises a pair of opposing straight-line portions, and arc-shape portions at both ends of the straight-line portions which connect the ends, so as to surround the collector electrode 10. Below, a closed planar shape comprising such straight-line portions and arc-shape portions is called a track shape. The emitter electrode 7 is formed in a track shape so as to surround the gate electrode 8. In this layout, the off-state breakdown voltage and on-state breakdown voltage are lower in the arc-shape portions.
To address this, it has been proposed that the length L2 of the n− drift regions 3 of the arc-shape portions be made longer than the length L1 of the n− drift regions 3 of the straight-line portions (see for example Japanese Patent Application Laid-open No. 6-244412 (FIG. 10), corresponding to U.S. Pat. No. 5,523,599A). And, it has been proposed that the channels of the arc-shape portions be made inactive (see for example Japanese Patent Publication No. 3473460 (paragraph [0011], FIG. 1, corresponding to U.S. Pat. No. 6,441,432 B1), Japanese Patent Application Laid-open No. 2007-96143 (FIG. 1), corresponding to US Patent No. 2007075393 A1). It has also been proposed that a potential-fixing region, in which the potential is fixed, be provided in an adjacent region adjacent to the drain region, formed in a stripe shape, with a dielectric isolation region intervening, to prevent fluctuations in the breakdown characteristics of the lateral semiconductor element due to potential fluctuations in a peripheral element (see for example Japanese Patent Application Laid-open No. 2006-210865 (FIG. 1)). And, it has been proposed that the threshold value of the arc-shape portions be made higher than the threshold value of the straight-line portions (see for example Japanese Patent Application Laid-open No. 2006-237474 (“Means of Solution” in “Abstract”). On the other hand, a multichannel-structure IGBT has been reported having a plurality of channel regions for a single collector region (see for example Hideyuki Funaki and four others, “Multi-Channel SOI Lateral IGBTS with Large SOA”, Int. Symp. Power Semiconductor Devices and ICs, 1997, pp. 33-36; Norio Yasuhara and three others, “Experimental Verification of Large Current Capability of Lateral IEGTs on SOI”, Int. Symp. Power Semiconductor Devices and ICs, 1996, pp. 97-100; and “Challenging the Limits of Power Device Silicon”, Inst. Elec. Eng. Jpn. Tech. Rep., No. 842, p. 85).
FIG. 55 is a cross-sectional view showing the configuration of a multichannel-structure IGBT of the prior art. As shown in FIG. 55, the n+ first emitter region 6a and n+ second emitter region 6b are provided, separated, in the surface region of the same p base region 4. The first gate electrode 8a is provided, with the first gate insulating film 9c intervening, on the surface of the p base region 4 between the n+ first emitter region 6a and the n− drift region 3. The second gate electrode 8b is provided, with the second gate insulating film 9d intervening, on the surface of the p base region 4 between the n+ second emitter region 6b and the n− drift region 3. The emitter electrode 7 is in contact with the n+ first emitter region 6a, n+ second emitter region 6b, and the p+ contact region 5.
However, in the above-described technology of the prior art, there are the following problems. In the structure of the prior art shown in FIG. 53, there is the drawback that when the isolation silicon region 14 is not present, or when the potential of the isolation silicon region 14 is floating, the electrostatic potential of an adjacent device exerts an influence. On the other hand, when the isolation silicon region 14 is fixed at a specific potential, whether in the on state or the off state, the extent of depletion of the n− drift region differs in the cell positioned adjacent to the isolation trench 13 (hereafter called an end cell) and in the cell positioned closer to the center (hereafter called a center cell). In an end cell, depletion occurs from the isolation silicon region 14, p base region, and supporting substrate. On the other hand, in a center cell, depletion occurs from the p base region and supporting substrate. Hence the breakdown voltage is determined by the center cell when the n− drift region concentration is high, and is determined by the end cell when the supporting substrate concentration is high.
In the case of an IGBT having the conventional structure shown in FIG. 53, the extent of depletion in the n− drift region is different in the off state and in the on state. In the on state, holes are injected from the p+ collector region to the n− drift region. Electrons are injected from the channel at the interface between the p base region and the gate insulating film into the n− drift region. The electric field distribution in the n− drift region is determined by equation (1) below. Here E is the electric field intensity, ∇ is a spatial derivative, ∇·E is the divergence of the electric field, ND+ is the space charge density in the n− drift region, p is the density of holes injected from the collector, n is the density of electrons injected from the channel, and ∈ is the dielectric constant.∇·E=(−ND++p−n)/∈  (1)
In the portion of the n− drift region close to the collector region, the number of holes is greater than the number of electrons, so that the n− drift region is not readily depleted. In order to raise the on-state breakdown voltage, the isolation silicon region 14 surrounded by the trench isolation portion may be set to the same potential as the emitter, to utilize depletion from the isolation silicon region 14. However, in the case of the center cell, depletion from the isolation silicon region 14 cannot be utilized, and so the breakdown voltage is unbalanced, and the breakdown voltage is determined by either the end cell or by the center cell.
In Japanese Patent Publication No. 3473460 (paragraph [0011], FIG. 1, corresponding to U.S. Pat. No. 6,441,432 B1) and Japanese Patent Application Laid-open No. 2007-96143 ((FIG. 1), corresponding to US Patent No. 2007075393 A1), there are concerns that the breakdown voltage cannot be increased. When the n− drift region concentration is low, the breakdown voltage is determined by the arc-shape portions of the track shape. This is explained as follows, referring to FIG. 56 and FIG. 57. FIG. 56 and FIG. 57 are explanatory diagrams explaining the fact of determination of the breakdown voltage by the arc-shape portions. FIG. 56 is a plane view showing the arc shape planar layout corresponding to the arc-shape portions, and FIG. 57 is a plane view showing the straight line-shape planar layout corresponding to the structure shown in FIG. 56.
As shown in FIG. 56, in the arc structure the p+ collector region 12 is surrounded on the outside by the n buffer region 11, the outside of this is surrounded by the n− drift region 3, the outside of this is further surrounded by the p base region 4, and the outside of this is further surrounded by the n+ emitter region 6, in a portion of a concentric-circle structure forming a fan shape. In the straight-line structure shown in FIG. 57, the p+ collector region 12, n buffer region 11, n− drift region 3, p base region 4, and n+ emitter region 6 are arranged in straight-line shapes, in this order. In both of these structures, although not shown, a gate insulating film and gate electrode are arranged above the p base region 4, a portion of the n− drift region 3, and a portion of the n+ emitter region 6.
In the arc structure, compared with the straight-line structure, the area of the p base region 4 is larger, and the area of the n− drift region 3 is smaller. Hence when a high voltage is applied to the p+ collector region 12, there is more depletion in the n− drift region 3 of the arc structure than in the n− drift region 3 of the straight-line structure. Hence if the concentration in the n− drift region 3 is determined such that the breakdown voltage of the straight-line structure is optimal, the electric field at the interface of the n− drift region 3 and the n buffer region 11 in the arc structure reaches the critical electric field intensity for silicon. As a result, elements with an arc structure fail before failure of elements having straight-line structures.
In the on state in which a channel is formed at the surface of the p base region 4, when a high voltage is applied to the p+ collector region 12, the current density is comparatively uniform in the n− drift region 3 of the straight-line structure. On the other hand, in the arc structure, the current density in the n− drift region 3 gradually rises on approaching the n buffer region 11. As a result, the effects of collision ionization are more severe in the arc structure than in the straight-line structure, and failure occurs more readily on the on state. If a large-current device with a high breakdown voltage is designed such that over the range of use there is no inversion of the sign of the right-hand side of equation (1) above, then the cause of failure is collision ionization, and not the Kirk effect. Hence if the extent of depletion in the n− drift region 3 is improved, and collision ionization is suppressed, then the on-state breakdown voltage can be maintained even when current concentration occurs due to the above-described arc-shape planar layout.
The structure disclosed in the above-described Japanese Patent Application Laid-open No. 6-244412 ((FIG. 10), corresponding to U.S. Pat. No. 5,523,599A) has the drawback that the cell area is increased, due to lengthening of the drift region in the arc portions. And, the structure disclosed in Japanese Patent Application Laid-open No. 2006-237474 (“Means of Solution” in “Abstract”) has the drawback of a reduced current capacity. On the other hand, it is readily inferred that by applying the multichannel structure shown in FIG. 55 to a track-shape planar layout structure such as that shown in FIG. 54, the current capacity can be improved. The various problems described above are not limited to cases in which SOI substrates are used, but similarly occur in cases of general substrates in which there is no buried insulating layer.